1. Field of the Invention
The present invention relates to semiconductor devices and more specifically to complementary devices fabricated on a common silicon-on-insulator (SOI) substrate and configured for minimizing leakage currents.
2. Description of Related Art
Complementary metal oxide silicon (CMOS) devices fabricated on silicon-on-insulator (SOI) substrates have advantages of high speed, high circuit packing density, latch up freedom and radiation hardening. Nevertheless, as device geometries are scaled down to one micron and sub-micron levels, leakage greatly increases. Floating substrates, impact ionizations, bi-polar effect, punch throughs, body effect, back channel turn-ons, zener diode breakdowns, hot electron degradation and the like all contribute to the high leakages in such devices. Leakages on high speed sub-micron silicon-on-insulator devices are much higher because of likelihood of back channel device turn-ons with a fixed substrate bias. By more heavily doping the depletion area between the source and drain, leakage can be reduced. However, this makes the transistor more difficult to turn on, and, in addition, provides lower operating voltages. It also may require a thinner depletion layer and decrease speed of the devices.
In devices of this type the complementary transistors are fabricated on a common substrate, such as, for example, a silicon N-substrate. Backgate biasing of such devices, as by application of voltage to the N-substrate, is desirable to minimize leakage and prevent soft turn-ons.
In attempting to reduce leakage in the CMOS/SOI devices, a positive voltage applied directly to the Nsilicon substrate, which is separated from the depletion region of the P channel transistor by a silicon oxide layer, can provide a voltage of a magnitude appropriate for control of leakage of the P channel device. However, because the adjoining N channel device is on the same N-silicon substrate, a positive voltage applied to the substrate will tend to cause conduction rather than reduced leakage of the N channel transistor. Thus it is common to reduce the desired level of positive backgate bias of the P channel transistor as a compromise with the desire to avoid unwanted conduction of the N channel transistor. Moreover, this necessity of balancing backgate bias for the two complementary adjacent transistors imposes limitations on processing conditions which increase the difficulty of the processing if the unwanted leakage is to be minimized.
Accordingly, it is an object of the present invention to provide CMOS devices fabricated on silicon-on-insulator substrates that minimize or eliminate above mentioned problems.